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? semiconductor components industries, llc, 2015 april, 2017 ? rev. 0 1 publication order number: ncv47722/d ncv47722 high side switch with adjustable current limit and diagnostic features the ncv47722 high side switch (hss) with 250 ma is designed for use in harsh automotive environments. the device has a high peak input voltage tolerance and reve rse input voltage, reverse bias, overcurrent and overtemperature protections. the integrated current sense feature (adjustable by resist or connected to cso pin) provides diagnosis and system protection functionality. the cso pin output current creates voltage drop across cso resistor which is proportional to output current. extended diagnostic features in off state are also available and controlled by dedicated input and output pins. features ? output current: up to 250 ma ? enable input (3.3 v logic compatible) ? adjustable current limit: up to 350 ma ? protection features: ? current limitation ? thermal shutdown ? reverse input voltage and reverse bias voltage ? diagnostic features: ? short to battery (stb) and open load (ol) in off state ? internal components for off state diagnostics ? open collector flag output ? output voltage monitoring output (analog) ? aec?q100 grade 1 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? audio and infotainment system ? active safety system figure 1. application schematic v out gnd v in cso en c in c out r cso c cso 1 f 1 f ncv47722 1 f de ef diagnostic enable input error flag output (open collector) v out_fb to a/d *vout_fb is sensed vout output voltage via internal resistor divider this document contains information on some products that are still under development. on semiconductor reserves the right to change or discontinue these products without notice. www. onsemi.com marking diagram ordering information see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. tssop?14 exposed pad case 948aw ncv4 7722 alyw 1 14 1 14 1 8 so?8 exposed pad pd suffix case 751ac (in development) 1 8 47722 alyw 47722 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package 47722 alyw 1 (note: microdot may be in either location) 1 dfn8 mnw suffix case 506by (in development) 1 8 so?8 d suffix case 751 (in development) 47722 alyw 1 8
ncv47722 www. onsemi.com 2 figure 2. simplified block diagram 2.55 v voltage reference thermal shutdown saturation protection en cso pass device and current mirror de ipu_on ef stb_ol_off gnd + ? + ? 0.95x stb_ol_off oc_on + ? diagnostic control logic oc_on pd_on en en enable pd_on 500k 100k 1.05 v 780k 780k 10 ma ipu_on *) for current value of ratio see into electrical characteristic table v ref v ref_off v in i pu r pd_on r pd_de v out v ref i cso = i out / ratio* v ref r pd1 r pd2 v ref_off v out_fb
ncv47722 www. onsemi.com 3 epad nc nc nc gnd en cso 4 1 1 nc nc ef de figure 3. pin connections (top views) nc dfn8 ef de gnd en cso ef de gnd en cso so?8, so?8 epad tssop?14 epad 18 18 v out v out_fb v in v out v out_fb v in v out v out_fb v in table 1. pin function description pin no. tssop?14 epad pin no. so?8 pin no. so?8 epad, dfn8 pin name description 1 ? ? nc not connected, not internally bonded. 2 ? ? nc not connected, not internally bonded. 3 ? ? nc not connected, not internally bonded. 4 2 2 gnd power supply ground. 5 3 3 en enable input; low level disables regulator. (used also for off state diagnos- tics control. 6 4 4 cso current sense output, current limit setting and output current value informa- tion. see application section for more details. 7 5 5 v in power supply input. 8 8 8 v out regulated output voltage. 9 1 1 v out_fb output voltage analog monitoring. see application section for more details. 10 6 6 de diagnostic enable input. 11 7 7 ef error flag (open collector) output. active low. 12 ? ? nc not connected, not internally bonded. 13 ? ? nc not connected, not internally bonded. 14 ? ? nc not connected, not internally bonded. epad ? epad epad exposed pad is connected to ground. connect to gnd plane on pcb.
ncv47722 www. onsemi.com 4 table 2. maximum ratings rating symbol min max unit input voltage dc v in ?42 45 v input voltage (note 1) load dump ? suppressed u s* ? 60 v enable input voltage v en ?42 45 v output voltage monitoring v out_fb ?0.3 10 v cso voltage v cso ?0.3 7 v de, cs and ef voltages v de , v cs , v ef ?0.3 7 v output voltage v out ?1 40 v junction temperature t j ?40 150 c storage temperature t stg ?55 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. load dump test b (with centralized load dump suppression) according to iso16750?2 standard. guaranteed by design. not tested in production. passed class a according to iso16750?1. table 3. esd capability (note 2) rating symbol min max unit esd capability, human body model esd hbm ?2 2 kv 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (js?001?2010) field induced charge device model esd characterization is not performed on plastic molded packages with body sizes < 50 mm 2 due to the inability of a small package body to acquire and retain enough charge to meet the minimum cdm discharge current waveform characteristic defined in jedec js?002?2014. table 4. lead soldering temperature and msl (note 3) rating symbol min max unit moisture sensitivity level msl 1 ? 3. for more information, please refer to our soldering and mounting techniques reference manual, solderrm/d thermal characteristics (note 4) rating symbol value unit thermal characteristics (single layer pcb) thermal resistance, junction?to?air (note 5) thermal reference, junction?to?lead (note 5) r ja r jl 62.6 23.7 c/w thermal characteristics (4 layers pcb) thermal resistance, junction?to?air (note 5) thermal reference, junction?to?lead (note 5) r ja r jl 44.1 16.8 c/w 4. refer to electrical characteristics and application information for safe operating area. 5. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. single layer ? according to jedec51.3, 4 layers ? according to jedec51.7 table 5. recommended operating ranges rating symbol min max unit input voltage (note 6) v in 4.4 40 v output current limit (note 7) i lim 10 350 ma junction temperature t j ?40 150 c current sense output (cso) capacitor c cso 1 4.7 f functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 6. minimum v in = 4.4 v or (v out + 0.5 v), whichever is higher. 7. corresponding r cso is in range from 76.5 k down to 2185 .
ncv47722 www. onsemi.com 5 table 6. electrical characteristics v in = 13.5 v, v en = 3.3 v, r cso = 0 , c cso = 1 f, c in = 1 f, c out = 1 f, min and max values are valid for temperature range ?40 c t j +150 c unless noted otherwise and are guaranteed by test, design or statistical correlation. typical values are referenced to t j = 25 c (note 8) parameter test conditions symbol min typ max unit outputs input to output differential voltage v in = 8 v to 18 v i out = 200 ma i out = 250 ma v in?out ? ? 200 225 350 400 mv current limit protection current limit v out = v in ? 1 v i lim 350 ? ? ma disable and quiescent currents disable current v en = 0 v i dis ? 0.002 10 a quiescent current, i q = i in ? i out i out = 500 a, v in = 8 v to 18 v i q ? 0.5 1.3 ma quiescent current, i q = i in ? i out i out = 200 ma, v in = 8 v to 18 v i q ? 8 19 ma quiescent current, i q = i in ? i out i out = 250 ma, v in = 8 v to 18 v i q ? 11 25 ma enable enable input threshold voltage logic low (off) logic high (on) v out 0.1 v v out v in ? 1 v v th(en) 0.99 ? 1.8 1.9 ? 2.31 v enable input current v en = 3.3 v i en 2 9 20 a turn on time from enable on to v out = v in ? 1 v i out = 100 ma t on ? 25 ? s output current sense cso voltage level at current limit v out = v in ? 1 v r cso = 3.3 k v cso_ilim 2.448 (?4%) 2.55 2.652 (+4%) v cso transient voltage level c cso = 4.7 f, r cso = 3.3 k i out pulse from 10 ma to 350 ma, tr = 1 s v cso ? ? 3.3 v output current to cso current ratio v cso = 2 v, i out = 10 ma to 50 ma v in = 8 v to 18 v, ?40 t j +150 i out /i cso ? (?15%) 265 ? (+15%) ? output current to cso current ratio v cso = 2 v, i out = 50 ma to 350 ma v in = 8 v to 18 v, ?40 t j +150 i out /i cso ? (?5%) 285 ? (+5%) ? cso current at no load current v cso = 0 v, i out = 0 ma i cso_off ? ? 15 a diagnostics overcurrent voltage level threshold v out = v in ? 1 v r cso = 3.3 k v oc 92 95 98 % of v cso_ ilim short to battery (stb) voltage threshold in off state v in = 4.4 v to 18 v, i out = 0 ma v stb 2 3 4 v open load (ol) current threshold in off state v in = 4.4 v to 18 v i ol 5 10 25 ma output voltage to output feedback voltage ratio v in = 4.4 v to 18 v v out /v outfb 5.7 6 6.3 ? diagnostics enable threshold voltage logic low (off) logic high (on) v th(de) 0.99 ? 1.8 1.9 ? 2.31 v error flag low voltage i ef = ?1 ma v ef_low ? 0.04 0.4 v thermal shutdown thermal shutdown temperature (note 9) i out = 90 ma t sd 150 175 195 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 8. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t a t j . low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 9. values based on design and/or characterization.
ncv47722 www. onsemi.com 6 typical characteristics figure 4. input to output differential voltage vs. temperature figure 5. input to output differential voltage vs. output current t j , junction temperature ( c) i out , output current (ma) 140 100 80 60 40 0 ?20 ?40 0 350 300 250 200 150 100 50 0 0 50 100 150 200 300 350 400 figure 6. output current limit vs. input voltage figure 7. input current vs. input voltage (reverse input voltage) v in , input voltage (v) v in , input voltage (v) 40 35 30 20 15 10 5 0 500 550 600 650 700 800 850 900 ?5 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 figure 8. output current limit vs. r cso figure 9. cso voltage vs. output current (% of i lim ) r cso (k ) i out , output current (% of i lim ) 70 60 50 40 30 20 10 0 0 50 100 150 200 300 350 400 90 80 70 50 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v in?out , input to output differential voltage (mv) i lim , output current limit (ma) i in , input current (ma) i lim , output current limit (ma) v cso , cso voltage (v) v out = (v in ? 1 v) v t j = 150 c t j = 25 c t j = ?40 c 25 45 750 t j = 25 c r out = 3.3 k ?10 0 t j = 150 c t j = 25 c t j = ?40 c v in = 13.5 v 400 250 20 120 160 v in?out , input to output differential voltage (mv) 50 100 150 200 300 350 400 250 v in = 13.5 v i out = 350 ma i out = 200 ma i out = 15 ma 80 250 40 60 100 110 t j = ?40 c to 150 c i lim = 10 ma to 350 ma
ncv47722 www. onsemi.com 7 typical characteristics figure 10. quiescent current vs. output current (low load) figure 11. quiescent current vs. output current (high load) i out , output current (ma) i out , output current (ma) 20 15 10 5 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 300 250 200 350 150 100 50 0 0 2 6 8 10 14 16 20 figure 12. output current to cso current ratio vs. output current i out , output current (ma) 1000 100 10 250 260 270 275 290 295 300 310 i q , quiescent current (ma) i q , quiescent current (ma) i out /i cso , output current to cso current ratio (?) 255 265 280 285 305 4 12 18 t j = 25 c v in = 13.5 v t j = 25 c v in = 13.5 v t j = 25 c v in = 13.5 v definitions general all measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature. input to output differential voltage the input to output differential voltage parameter is defined for specific output current values and specified over temperature range. quiescent and disable currents quiescent current (i q ) is the dif ference between the input current (measured through the ldo input pin) and the output load current. if enable pin is set to low the regulator reduces its internal bias and shuts off the output, this term is called the disable current (i dis ). current limit current limit is value of output current by which output voltage drops below 90% of its nominal value. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated at typically 175 c, the regulator turns off. this feature is provided to prevent failures from accidental overheating. maximum package power dissipation the power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower.
ncv47722 www. onsemi.com 8 applications information circuit description the ncv47722 is an integrated high side switch (hss) with output current capability up to 250 ma to output. it is enabled with an input to the enable pin. the integrated current sense feature provides diagnosis and system protection functionality. the current limit of the device is adjustable by resistor connected to cso pin. voltage on cso pin is proportional to output current. the hss is protected by both current limit and thermal shutdown. thermal shutdown occurs above 150 c to protect the ic during overloads and extreme ambient temperatures. enable input the enable pin is used to turn the regulator on or off. by holding the pin down to a voltage less than 0.99 v, the output of the regulator will be turned off. when the voltage on the enable pin is greater than 2.31 v, the output of the regulator will be enabled to power its output to the regulated output voltage. the enable pin may be connected directly to the input pin to give constant enable to the output regulator. setting the output current limit the output current limit can be set up to 350 ma by external resistor r cso (see figure 1). capacitor c cso of 1 f in parallel with r cso is required for stability of current limit control circuitry (see figure 1). v cso i out r cso 1 ratio (eq. 1) i lim ratio 2.55 r cso (eq. 2) r cso ratio 2.55 i lim (eq. 3) where r cso ? current limit setting resistor v cso - voltage at cso pin proportional to i out i lim ? current limit value i out ? output current actual value ratio ? typical value of output current to cso current ratio for particular output current range cso pin provides information about output current actual value. the cso voltage is proportional to output current according to equation 1. once output current reaches its limit value (i lim ) set by external resistor r cso than voltage at cso pin is typically 2.55 v. calculations of i lim or r cso values can be done using equation 2 and equation 3, respectively. minimum and maximum value of output current limit can be calculated according to equations 4 and 5. (eq. 4) i lim_min ratio min v cso_min r cso_max (eq. 5) i lim_max ratio max v cso_max r cso_min where ratio min ? minimum value of output current to cso current ratio from electrical characteristics table and particular output current range ratio max ? maximum value of output current to cso current ratio from electrical characteristics table and particular output current range v cso_min - minimum value of cso voltage level at current limit from electrical characteristics table v cso_max - maximum value of cso voltage level at current limit from electrical characteristics table r cso_min ? minimum value of r cso with respect its accuracy r cso_max ? maximum value of r cso with respect its accuracy designers should consider the tolerance of r cso during the design phase. diagnostic in off state the ncv47722 contains also circuitry for off state diagnostics for short to battery (stb) and open load (ol). there are internal current source and pull down resistors which provide additional cost savings for overall application by excluding external components and their assembly cost and saving pcb space and safe control ios of a microcontroller unit (mcu). simplified functional schematic and truth table is shown in figure 13 and related flowchart in figure 14.
ncv47722 www. onsemi.com 9 figure 13. simplified functional diagram of off state diagnostics (stb and ol) v out + ? v ref_off ef pass device is off in diagnostics mode in off state v in current source enabled via en and de pins comparator active only in diagnostic state (de = h). i pu en ? enable (logic input) de ? diagnostics enable (logic input) ef ? error flag output (open collector output) en de r pd1 r pd2 digital diagnostics: to mcu?s digital input with pull?up resistor to mcu?s dio supply rail en de i pu ef v out diagnostic status/action l l off hz unknown none (diagnostics off) l h off l v out > v out_off short to battery (stb) l h off hz v out < v out_off check for open load (ol) hhonlv out > v out_off open load (ol) h h on hz v out < v out_off no failure (v out close to 0 v) for diagnostics in off state the input de pin has to be put logic high. logic level on en pin determines which failure (stb or ol) is diagnosed. for detailed information see diagnostic truth table 7. diagnostic in on state diagnostic in on state provides information about overcurrent or short to ground failures, during which the ef output is in logic low state. for detailed information see diagnostic features truth table 7. start diag. off. set en = l & de = l ef = ? diag. on. set en = l & de = h l hz ef = ? l hz no failure open load short to battery figure 14. flowchart for diagnostics in off state i pu on. set en = h & de = h table 7. diagnostic features truth table operational status en de output voltage (v out ) diagnostic output (cso) error flag (ef) disabled l l low (~0 v) low (~0 v) hz short to battery l h high (v out ~ v in ) low (~0 v) l (note 10) open load (off) h h high (v out ~ v in ) low (~0 v) l (note 11) normal (off) h h low (~0 v) low (~0 v) hz (note 11) open load (on) h l high (v out ~ v in ) low (~0 v) hz normal (on) h l high (v out ~ v in ) proportional to i out ( 5%) (note 12) hz over current h l v in ? 1 v high (~2.55 v) l short to ground h l low (~0 v) high (~2.55 v) l 10. internal current source disabled (between v out and v in ). 11. internal current source enabled (between v out and v in ). 12. valid for i out = 50 ma to 350 ma. for i out = 10 ma to 50 ma range proportional to i out ( 15%).
ncv47722 www. onsemi.com 10 thermal considerations as power in the device increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the device has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the device can handle is given by: p d(max) t j(max)
t a r ja (eq. 6) since t j is not recommended to exceed 150 c, then the device soldered on 645 mm 2 , 1 oz copper area, fr4 can dissipate up to 2 w when the ambient temperature (t a ) is 25 c. see figure 15 for r ja versus pcb area. the power dissipated by the device can be calculated from the following equations: p d v in i q @i out i out v in
v out (eq. 7) or v in(max) p d(max) v out i out i out i q (eq. 8) figure 15. thermal resistance vs. pcb copper area copper heat spreader area (mm 2 ) 600 700 500 400 300 200 100 0 20 30 50 70 80 100 110 r ja , thermal resistance ( c/w) 40 60 90 120 1 oz, single layer 2 oz, single layer 1 oz, 4 layer 2 oz, 4 layer hints v in and gnd printed circuit board traces should be as wide as possible. when the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. place external components, especially the output capacitor, as close as possible to the device and make traces as short as possible. ordering information device output voltage marking package shipping ? ncv47722paajr2g adjustable line1: ncv4 line2: 7722 tssop?14 exposed pad (pb?free) 2500 / tape & reel ncv47722pdajr2g (in development) adjustable 47722 soic?8 ep (pb?free) 2500 / tape & reel ncv47722dajr2g (in development) adjustable 47722 soic?8 (pb?free) 2500 / tape & reel NCV47722MNWTXG (in development) adjustable 47722 dfn8 with wettable flanks (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d
ncv47722 www. onsemi.com 11 package dimensions tssop?14 ep case 948aw issue c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.07 mm max. at maximum material condition. dambar cannot be located on the lower radi- us of the foot. minimum space between pro- trusion and adjacent lead is 0.07. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. dimension d is determined at datum h. 5. dimension e1 does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.25 mm per side. dimension e1 is determined at datum h. 6. datums a and b are determined at datum h. 7. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 8. section b?b to be determined at 0.10 to 0.25 mm from the lead tip. dim min max millimeters a ???? 1.20 b 0.19 0.30 c 0.09 0.20 a1 0.05 0.15 l 0.45 0.75 m 0 8 6.70 14x 0.42 14x 1.15 0.65 dimensions: millimeters 1 pitch soldering footprint e 6.40 bsc l2 0.25 bsc recommended 3.06 3.40 ??? ??? ??? section b?b c c1 b b1 0.80 1.05 b1 0.19 0.25 c1 0.09 0.16 d 4.90 5.10 d2 3.09 3.62 e1 4.30 4.50 e2 2.69 3.22 0.65 bsc e seating plane a2 m l detail a end view pin 1 7 1 14 8 top view e1 side view reference 0.20 c note 5 2x 14 tips b 0.10 c c a 14x c detail a a1 b b e2 bottom view d2 b 0.10 c note 3 b a 14x 0.05 c d note 4 gauge plane c note 7 h l2 e e ba note 6 note 8 a note 6 s s
ncv47722 www. onsemi.com 12 package dimensions soic?8 nb case 751?07 issue ak (in development) seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncv47722 www. onsemi.com 13 package dimensions case 751ac issue b (in development) ?? ?? ?? h c 0.10 d e1 a d pin one 2 x 8 x seating plane exposed gauge plane 14 5 8 d c 0.10 a-b 2 x e b e c 0.10 2 x top view side view bottom view detail a end view section a?a 8 x b a-b 0.25 d c c c 0.10 c 0.20 a a2 g f 1 4 58 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters (angles in degrees). 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the ?b? dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. dim min max millimeters a 1.35 1.75 a1 0.00 0.10 a2 1.35 1.65 b 0.31 0.51 b1 0.28 0.48 c 0.17 0.25 c1 0.17 0.23 d 4.90 bsc e 6.00 bsc e 1.27 bsc l 0.40 1.27 l1 1.04 ref f 2.24 3.20 g 1.55 2.51 h 0.25 0.50 0 8 h aa detail a (b) b1 c c1 0.25 l (l1) pad e1 3.90 bsc a1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* location exposed pad 1.52 0.060 2.03 0.08 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 7.0 0.275 2.72 0.107
ncv47722 www. onsemi.com 14 package dimensions dfn8, 3x3, 0.65p case 506by issue a (in development) notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 5. for device opn containing w option, detail b alternate construction is not applicable. a b e d d2 e2 bottom view b e 8x 0.10 b 0.05 a c c k 8x note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 14 5 8 dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 3.00 bsc d2 2.20 2.40 e 3.00 bsc e2 1.40 1.60 e 0.65 bsc k 0.20 ??? l 0.20 0.40 ? ? ?? ?? ?? ?? ?? ?? ? ? ?? ?? ?? ?? ?? ?? 1 0.65 pitch 3.30 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 8x dimensions: millimeters l1 detail a l alternate constructions l detail b detail a l1 0.00 0.15 note 4 e/2 soldering footprint* ??? ??? ?? on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv47722/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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